BEGIN:VCALENDAR VERSION:2.0 PRODID:-//DATE2026//date-conference.com//EN CALSCALE:GREGORIAN METHOD:PUBLISH BEGIN:VEVENT DTSTART;TZID=Europe/Rome:20260421T083000 DTEND;TZID=Europe/Rome:20260421T123000 LOCATION:Room Bohème CREATED:20260421T174602 DTSTAMP:20260421T174602 SUMMARY:W04 Rapid Design Space Explorations of Novel Hardware Solutions: from Atoms to Applications URL;VALUE=URI:https://date26date-conference.com/programme#W04 BEGIN:VALARM TRIGGER:-PT15M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM DESCRIPTION:Get the latest session information at https://date26date-conference.com/programme#W04\n\n\nOrganisers: Michael Niemier, Ian O'Connor, Siddharth Joshi and Lorenzo Ciampolini (mniemier@nd.edu) – United States & France\n \n At a high-level, there is a need to integrate physics-aware models of non-volatile memories (NVMs), thermal properties of silicon and memory devices, and advances with interconnect and packaging solutions (e.g., chiplets) with system-level architectural exploration. Device-centric work can be informed by AI-guided materials discovery efforts and tooling, while compilers-centric work will provide paths to programmability for novel hardware solutions. The resulting impact of this cyber-infrastructure would be many-fold. (1) Researchers at lower-levels of the design stack can use said tools to evaluate the efficacy of novel materials/devices on application-level workloads, thereby prioritizing efforts in said space; (2) researchers at higher-levels of the design stack can (a) be in-formed by the practical capabilities of novel hardware solutions (which can subsequently guide research at the architectural and/or algorithmic levels) and (b) be used to sweep a range of opti-mistic and pessimistic assumptions for novel devices to more rapidly identify “thresholds” for FOM that are ultimately required to positively impact application-level performance from the top-down. The workshop will capture the scope of this vast design space, identify existing infrastructure from the research community that may address the above challenges, identify gaps and/or ways to link seemingly disparate design tools to address said gaps, while simultaneously identifying news ways for the design automation community to focus research that spans from the atomistic to the application-level.\n \n More technically, this workshop will capture how modeling various aspects of NVMs, 2.5D/3D interconnects, and architectures including thermal, electrical, and analytical models, can be inte-grated into design space exploration (DSE) tools such as Timeloop and ZigZag. Talks will discuss how to enhance existing DSE frameworks to facilitate modeling for next-generation accelerator use (e.g., thermally/chiplet-aware map spaces) to best meet the needs of future users. Among others, presentations will consider how to integrate/refine analytical models for novel memory systems across various abstraction levels, and how models can be calibrated with detailed device, inter-connect, and thermal modeling to inform the toolset across abstraction layers. (The latter will also encompass emerging research threads such as AI-guided materials discovery to accelerate the development of logic, memory, and interconnect technologies that can achieve key performance indi-cators that are necessary to satisfactorily address the compute requirements of emerging work-loads.) We will also consider how cycle-accurate architectural simulators could be employed in conjunction with Timeloop/ZigZag to study chipsets such as a highly multi-threaded CPU, a high-end GPU, and/or a neural engine, as well as optimal data mapping strategies. Compilers-based infrastructure will map compute kernels from machine learning (ML) APIs such as TensorFlow and PyTorch and can drive research from the bottom-up or top-down.\n \n The workshop will architect a path toward an infrastructure that will deliver an enhanced, extensi-ble analytical modeling toolset, validated models, and actionable design insights. Said frameworks will afford the academic community at large, as well as industrial partners who work at all levels of the design stack with the capability to quantitatively evaluate/co-design next-generation memory systems with advanced workloads. X-ALT-DESC;FMTTYPE=text/html:

Get the latest session information at https://date26date-conference.com/programme#W04

Organisers: Michael Niemier, Ian O'Connor, Siddharth Joshi and Lorenzo Ciampolini (mniemier@nd.edu) – United States & France
 

At a high-level, there is a need to integrate physics-aware models of non-volatile memories (NVMs), thermal properties of silicon and memory devices, and advances with interconnect and packaging solutions (e.g., chiplets) with system-level architectural exploration. Device-centric work can be informed by AI-guided materials discovery efforts and tooling, while compilers-centric work will provide paths to programmability for novel hardware solutions. The resulting impact of this cyber-infrastructure would be many-fold. (1) Researchers at lower-levels of the design stack can use said tools to evaluate the efficacy of novel materials/devices on application-level workloads, thereby prioritizing efforts in said space; (2) researchers at higher-levels of the design stack can (a) be in-formed by the practical capabilities of novel hardware solutions (which can subsequently guide research at the architectural and/or algorithmic levels) and (b) be used to sweep a range of opti-mistic and pessimistic assumptions for novel devices to more rapidly identify “thresholds” for FOM that are ultimately required to positively impact application-level performance from the top-down.  The workshop will capture the scope of this vast design space, identify existing infrastructure from the research community that may address the above challenges, identify  gaps and/or ways to link seemingly disparate design tools to address said gaps, while simultaneously identifying news ways for the design automation community to focus research that spans from the atomistic to the application-level.

More technically, this workshop will capture how modeling various aspects of NVMs, 2.5D/3D interconnects, and architectures including thermal, electrical, and analytical models, can be inte-grated into design space exploration (DSE) tools such as Timeloop and ZigZag.  Talks will discuss how to enhance existing DSE frameworks to facilitate modeling for next-generation accelerator use (e.g., thermally/chiplet-aware map spaces) to best meet the needs of future users. Among others, presentations will consider how to integrate/refine analytical models for novel memory systems across various abstraction levels, and how models can be calibrated with detailed device, inter-connect, and thermal modeling to inform the toolset across abstraction layers. (The latter will also encompass emerging research threads such as AI-guided materials discovery to accelerate the development of logic, memory, and interconnect technologies that can achieve key performance indi-cators that are necessary to satisfactorily address the compute requirements of emerging work-loads.)  We will also consider how cycle-accurate architectural simulators could be employed in conjunction with Timeloop/ZigZag to study chipsets such as a highly multi-threaded CPU, a high-end GPU, and/or a neural engine, as well as optimal data mapping strategies. Compilers-based infrastructure will map compute kernels from machine learning (ML) APIs such as TensorFlow and PyTorch and can drive research from the bottom-up or top-down.

The workshop will architect a path toward an infrastructure that will deliver an enhanced, extensi-ble analytical modeling toolset, validated models, and actionable design insights. Said frameworks will afford the academic community at large, as well as industrial partners who work at all levels of the design stack with the capability to quantitatively evaluate/co-design next-generation memory systems with advanced workloads.
 

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