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DTSTART;TZID=Europe/Rome:20260420T094500
DTEND;TZID=Europe/Rome:20260420T103000
LOCATION:Room Auditorium
CREATED:20260421T174602
DTSTAMP:20260421T174602
SUMMARY:OK02 Opening Keynote "Ultra-Low Latency Real-Time Processing for Quantum Computing"
URL;VALUE=URI:https://date26date-conference.com/programme#OK02
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DESCRIPTION:Reminder
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DESCRIPTION:Get the latest session information at 
	https://date26date-conference.com/programme#OK02\n\n\nQuantum computing is 
	one of the most promising technologies of our era. The fundamentally 
	different nature of quantum processors (QPUs) requires a highly 
	interdisciplinary effort to tackle challenges across the entire system to 
	effectively leverage quantum resources. To realise the commercial 
	potential of quantum acceleration, significant HPC resources are required 
	to accelerate workloads necessary to the operation of a QPU. These 
	workloads involve tasks related to quantum error correction, system 
	calibration, and optimal control, and hence require an ultra-low latency 
	exchange between the quantum system controllers (QSCs) and traditional 
	processors such as GPUs.\nIntroducing a tight coupling between HPC and QPU 
	environment presents a number of challenges that have become a focus 
	within the quantum-HPC community.\nMost QSCs are implemented using FPGAs 
	or RFSoC devices, which run a firmware-defined pulse processor unit (PPU). 
	Connecting the QSC via PCIe card can enable direct communication but poses 
	scaling challenges. A potentially preferable alternative that offers 
	better options for distribution is the use of a network interface card 
	(NIC) for connection via Ethernet or InfiniBand.\nIn this talk I will 
	discuss NVIDIA's effort to facilitate the development of advanced QPUs 
	using real-time processing on GPUs using the NVQLink architecture. NVQLink 
	leverages the RDMA over Converged Ethernet (RoCE) protocol to bypass 
	traditional network stacks and CPU involvement, enabling sub-microsecond 
	data transfer. This is essential to achieve real-time quantum error 
	correction, where latency tolerances are of the order of tens of 
	microseconds for some QPU architectures. While most existing solutions are 
	limited to using FPGA for real-time processing, the availability of 
	real-time compute on GPUs greatly facilitates the use of machine learning 
	and AI for automation and accuracy improvements. First realisations of 
	NVQLink systems thus enable a big step forward towards achieving fault 
	tolerant quantum computing at scale by enabling data-driven research and 
	co-develop of hardware and software solutions to achieve the necessary 
	throughput and latency for commercial applications.\nIntroducing a tight 
	coupling between HPC and QPU environment presents a number of challenges 
	that have become a focus within the quantum-HPC community.\n\nMost QSCs 
	are implemented using FPGAs or RFSoC devices, which run a firmware-defined 
	pulse processor unit (PPU). Connecting the QSC via PCIe card can enable 
	direct communication but poses scaling challenges. A potentially 
	preferable alternative that offers better options for distribution is the 
	use of a network interface card (NIC) for connection via Ethernet or 
	InfiniBand.\n\nIn this talk I will discuss NVIDIA's effort to facilitate 
	the development of advanced QPUs using real-time processing on GPUs using 
	the NVQLink architecture. NVQLink leverages the RDMA over Converged 
	Ethernet (RoCE) protocol to bypass traditional network stacks and CPU 
	involvement, enabling sub-microsecond data transfer. This is essential to 
	achieve real-time quantum error correction, where latency tolerances are 
	of the order of tens of microseconds for some QPU architectures. While 
	most existing solutions are limited to using FPGA for real-time 
	processing, the availability of real-time compute on GPUs greatly 
	facilitates the use of machine learning and AI for automation and accuracy 
	improvements. First realizations of NVQLink systems thus enable a big step 
	forward towards achieving fault tolerant quantum computing at scale by 
	enabling data-driven research and co-develop of hardware and software 
	solutions to achieve the necessary throughput and latency for commercial 
	applications.
X-ALT-DESC;FMTTYPE=text/html:<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"><HTML><HEAD><META 
	NAME="Generator" CONTENT="MS Exchange Server version 
	16.0.17231.20290"><TITLE></TITLE></HEAD><BODY><p>Get the latest session 
	information at <a 
	href="https://date26date-conference.com/programme#OK02">https://date26date-conference.com/programme#OK02</a></p><div>Quantum 
	computing is one of the most promising technologies of our era. The 
	fundamentally different nature of quantum processors (QPUs) requires a 
	highly interdisciplinary effort to tackle challenges across the entire 
	system to effectively leverage quantum resources. To realise the 
	commercial potential of quantum acceleration, significant HPC resources 
	are required to accelerate workloads necessary to the operation of a QPU. 
	These workloads involve tasks related to quantum error correction, system 
	calibration, and optimal control, and hence require an ultra-low latency 
	exchange between the quantum system controllers (QSCs) and traditional 
	processors such as GPUs.Introducing a tight coupling between HPC and QPU 
	environment presents a number of challenges that have become a focus 
	within the quantum-HPC community.Most QSCs are implemented using FPGAs or 
	RFSoC devices, which run a firmware-defined pulse processor unit (PPU). 
	Connecting the QSC via PCIe card can enable direct communication but poses 
	scaling challenges. A potentially preferable alternative that offers 
	better options for distribution is the use of a network interface card 
	(NIC) for connection via Ethernet or InfiniBand.In this talk I will 
	discuss NVIDIA's effort to facilitate the development of advanced QPUs 
	using real-time processing on GPUs using the NVQLink architecture. NVQLink 
	leverages the RDMA over Converged Ethernet (RoCE) protocol to bypass 
	traditional network stacks and CPU involvement, enabling sub-microsecond 
	data transfer. This is essential to achieve real-time quantum error 
	correction, where latency tolerances are of the order of tens of 
	microseconds for some QPU architectures. While most existing solutions are 
	limited to using FPGA for real-time processing, the availability of 
	real-time compute on GPUs greatly facilitates the use of machine learning 
	and AI for automation and accuracy improvements. First realisations of 
	NVQLink systems thus enable a big step forward towards achieving fault 
	tolerant quantum computing at scale by enabling data-driven research and 
	co-develop of hardware and software solutions to achieve the necessary 
	throughput and latency for commercial applications.Introducing a tight 
	coupling between HPC and QPU environment presents a number of challenges 
	that have become a focus within the quantum-HPC community.Most QSCs are 
	implemented using FPGAs or RFSoC devices, which run a firmware-defined 
	pulse processor unit (PPU). Connecting the QSC via PCIe card can enable 
	direct communication but poses scaling challenges. A potentially 
	preferable alternative that offers better options for distribution is the 
	use of a network interface card (NIC) for connection via Ethernet or 
	InfiniBand.In this talk I will discuss NVIDIA's effort to facilitate the 
	development of advanced QPUs using real-time processing on GPUs using the 
	NVQLink architecture. NVQLink leverages the RDMA over Converged Ethernet 
	(RoCE) protocol to bypass traditional network stacks and CPU involvement, 
	enabling sub-microsecond data transfer. This is essential to achieve 
	real-time quantum error correction, where latency tolerances are of the 
	order of tens of microseconds for some QPU architectures. While most 
	existing solutions are limited to using FPGA for real-time processing, the 
	availability of real-time compute on GPUs greatly facilitates the use of 
	machine learning and AI for automation and accuracy improvements. First 
	realizations of NVQLink systems thus enable a big step forward towards 
	achieving fault tolerant quantum computing at scale by enabling 
	data-driven research and co-develop of hardware and software solutions to 
	achieve the necessary throughput and latency for commercial 
	applications.</div></BODY></HTML>
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