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BEGIN:VEVENT
DTSTART;TZID=Europe/Rome:20260421T140000
DTEND;TZID=Europe/Rome:20260421T153000
LOCATION:Room Figaro
CREATED:20260421T174602
DTSTAMP:20260421T174602
SUMMARY:FS05 Focus Session: Beyond Conventional Hardware Security: Next-Generation Design and Security Evaluation for Hardware Architectures (HotTopic)
URL;VALUE=URI:https://date26date-conference.com/programme#FS05
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DESCRIPTION:Reminder
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DESCRIPTION:Get the latest session information at 
	https://date26date-conference.com/programme#FS05\n\n\nModern computing 
	systems depend on the trustworthiness of their underlying hardware, 
	par-ticularly the increasingly complex System-on-Chip (SoC) and CPU 
	architectures that power de-vices across cloud, edge, and IoT 
	environments. The attack surface has expanded dramatically as these 
	architectures integrate heterogeneous components into single, compact 
	dies, includ-ing processors, accelerators, and third-party IPs. In recent 
	years, academia and industry have reported numerous security-critical 
	vulnerabilities in commercial SoCs and CPUs, underscoring the urgent need 
	for scalable, automated techniques to detect hardware-level flaws before 
	fabrication. Unlike software vulnerabilities, hardware flaws are immutable 
	once silicon is produced, making pre-silicon security validation 
	technically essential and economical-ly critical. At the same time, the 
	exponential rise of Artificial Intelligence (AI) has revolutionized 
	compu-ting, driving an unprecedented demand for specialized hardware such 
	as GPUs and NPUs. These accelerators now form the backbone of AI 
	infrastructure used by governments, enter-prises, and research 
	institutions worldwide. Ensuring the security and integrity of these AI 
	hardware platforms is crucial, as their compromise could undermine model 
	reliability, data confidentiality, and national-scale AI systems. The 
	hardware foundations of AI must therefore be secure, verifiable, and 
	trustworthy to maintain the current pace of innovation. Interestingly, 
	this technological convergence also gives rise to a new paradigm, AI for 
	hard-ware security. Researchers have recently begun applying AI-driven 
	methodologies to enhance security validation, automate design-space 
	exploration, and detect vulnerabilities more effi-ciently. Leveraging 
	learning-based models, adaptive search strategies, and generative 
	tech-niques, AI is now reshaping how hardware security analysis is 
	performed. However, these same advancements also introduce novel risks, 
	such as adversarial manipulation of AI-guided verification tools or 
	unintended bias in automated test generation. This focus session will 
	present diverse perspectives from academia and industry on advanced 
	hardware security analysis techniques, the potential and challenges of 
	using AI to advance hardware security evaluation, and emerging risks and 
	mitigation strategies that accompany this evolution. Motivated by 
	long-term community efforts such as the HackTheSilicon hardware security 
	com-petitions, which, since 2018, have engaged in discovering 
	vulnerabilities in realistic SoCs, this session emphasizes how hands-on 
	insights and open evaluation frameworks are shaping the next generation of 
	secure hardware design. Together, these experiences highlight the growing 
	need for intelligence-driven, scalable, and proactive security validation 
	frameworks to protect the hardware that creates modern computing and AI 
	ecosystems. This Focus Session brings together leading experts from 
	academia and industry to explore emerging methodologies, case studies, and 
	research challenges in next-generation hardware security validation, 
	focusing on: 1.	Emerging vulnerabilities and security validation 
	challenges in SoCs, CPUs, and AI accel-erators. 2.	Hybrid hardware 
	verification techniques like formal-fuzzing and AI-guided valida-tion 
	techniques integrate symbolic reasoning with adaptive automation. 
	3.	AI-assisted hardware security techniques include learning-based 
	fuzzing, predictive bug detection, and automated verification. 4.	Risks 
	introduced by AI in hardware security workflows and potential 
	countermeasures for safe adoption. 5.	Collaborative directions toward 
	integrating security validation into standard hardware design and 
	verification pipelines. Through these discussions, the session will 
	deliver a holistic industry and academia view of advanced hardware 
	security verification methods, how AI depends on and enables hardware 
	security, and offer a roadmap for developing trustworthy systems.
X-ALT-DESC;FMTTYPE=text/html:<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"><HTML><HEAD><META 
	NAME="Generator" CONTENT="MS Exchange Server version 
	16.0.17231.20290"><TITLE></TITLE></HEAD><BODY><p>Get the latest session 
	information at <a 
	href="https://date26date-conference.com/programme#FS05">https://date26date-conference.com/programme#FS05</a></p><div>Modern 
	computing systems depend on the trustworthiness of their underlying 
	hardware, par-ticularly the increasingly complex System-on-Chip (SoC) and 
	CPU architectures that power de-vices across cloud, edge, and IoT 
	environments. The attack surface has expanded dramatically as these 
	architectures integrate heterogeneous components into single, compact 
	dies, includ-ing processors, accelerators, and third-party IPs. In recent 
	years, academia and industry have reported numerous security-critical 
	vulnerabilities in commercial SoCs and CPUs, underscoring the urgent need 
	for scalable, automated techniques to detect hardware-level flaws before 
	fabrication. Unlike software vulnerabilities, hardware flaws are immutable 
	once silicon is produced, making pre-silicon security validation 
	technically essential and economical-ly critical. At the same time, the 
	exponential rise of Artificial Intelligence (AI) has revolutionized 
	compu-ting, driving an unprecedented demand for specialized hardware such 
	as GPUs and NPUs. These accelerators now form the backbone of AI 
	infrastructure used by governments, enter-prises, and research 
	institutions worldwide. Ensuring the security and integrity of these AI 
	hardware platforms is crucial, as their compromise could undermine model 
	reliability, data confidentiality, and national-scale AI systems. The 
	hardware foundations of AI must therefore be secure, verifiable, and 
	trustworthy to maintain the current pace of innovation. Interestingly, 
	this technological convergence also gives rise to a new paradigm, AI for 
	hard-ware security. Researchers have recently begun applying AI-driven 
	methodologies to enhance security validation, automate design-space 
	exploration, and detect vulnerabilities more effi-ciently. Leveraging 
	learning-based models, adaptive search strategies, and generative 
	tech-niques, AI is now reshaping how hardware security analysis is 
	performed. However, these same advancements also introduce novel risks, 
	such as adversarial manipulation of AI-guided verification tools or 
	unintended bias in automated test generation. This focus session will 
	present diverse perspectives from academia and industry on advanced 
	hardware security analysis techniques, the potential and challenges of 
	using AI to advance hardware security evaluation, and emerging risks and 
	mitigation strategies that accompany this evolution. Motivated by 
	long-term community efforts such as the HackTheSilicon hardware security 
	com-petitions, which, since 2018, have engaged in discovering 
	vulnerabilities in realistic SoCs, this session emphasizes how hands-on 
	insights and open evaluation frameworks are shaping the next generation of 
	secure hardware design. Together, these experiences highlight the growing 
	need for intelligence-driven, scalable, and proactive security validation 
	frameworks to protect the hardware that creates modern computing and AI 
	ecosystems. This Focus Session brings together leading experts from 
	academia and industry to explore emerging methodologies, case studies, and 
	research challenges in next-generation hardware security validation, 
	focusing on: 1.	Emerging vulnerabilities and security validation 
	challenges in SoCs, CPUs, and AI accel-erators. 2.	Hybrid hardware 
	verification techniques like formal-fuzzing and AI-guided valida-tion 
	techniques integrate symbolic reasoning with adaptive automation. 
	3.	AI-assisted hardware security techniques include learning-based 
	fuzzing, predictive bug detection, and automated verification. 4.	Risks 
	introduced by AI in hardware security workflows and potential 
	countermeasures for safe adoption. 5.	Collaborative directions toward 
	integrating security validation into standard hardware design and 
	verification pipelines. Through these discussions, the session will 
	deliver a holistic industry and academia view of advanced hardware 
	security verification methods, how AI depends on and enables hardware 
	security, and offer a roadmap for developing trustworthy 
	systems.</div></BODY></HTML>
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