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DTSTART;TZID=Europe/Rome:20260421T083000
DTEND;TZID=Europe/Rome:20260421T100000
LOCATION:Room Figaro
CREATED:20260421T174602
DTSTAMP:20260421T174602
SUMMARY:FS03 Focus Session: Challenges and Perspectives in Advanced Packaging: Design, Reliability, and Security of 3D and Chiplet-Based Systems
URL;VALUE=URI:https://date26date-conference.com/programme#FS03
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DESCRIPTION:Get the latest session information at
https://date26date-conference.com/programme#FS03\n\n\nAI workloads are
driving exceptional demand for performance and energy efficiency, forcing
semiconductor inno- vation to advance along two major directions
simultaneously. On the device roadmap, the transition from FinFETs to
gate- all-around nanosheet FETs and, subsequently, monolithic 3D
Complementary FETs (CFETs) is enabling scaling toward the 2nm era and
beyond while targeting aggressive logic density. In parallel, advanced
packaging, spanning 2.5D integration on silicon interposers, true 3D
stacking, and hybrid 5.5D assemblies, is becoming essential to deliver
ultra-high bandwidth, low-energy die-to-die connectivity required by
rapidly growing AI model sizes and the resulting memory-wall bottlenecks.
This focus session discusses the opportunities and challenges of this
co-evolution, with emphasis on system-technology co-optimization and the
inevitable need for multiphysics analysis across electrical, thermal,
mechanical, and reliability domains. We highlight how reliability and
security concerns are increasingly shaping architectural and packaging
choices, and we discuss the role of deep learning as a practical enabler
for faster simulation and design-space exploration under rising
complexity.
X-ALT-DESC;FMTTYPE=text/html:Get the latest session
information at https://date26date-conference.com/programme#FS03
AI
workloads are driving exceptional demand for performance and energy
efficiency, forcing semiconductor inno- vation to advance along two major
directions simultaneously. On the device roadmap, the transition from
FinFETs to gate- all-around nanosheet FETs and, subsequently, monolithic
3D Complementary FETs (CFETs) is enabling scaling toward the 2nm era and
beyond while targeting aggressive logic density. In parallel, advanced
packaging, spanning 2.5D integration on silicon interposers, true 3D
stacking, and hybrid 5.5D assemblies, is becoming essential to deliver
ultra-high bandwidth, low-energy die-to-die connectivity required by
rapidly growing AI model sizes and the resulting memory-wall bottlenecks.
This focus session discusses the opportunities and challenges of this
co-evolution, with emphasis on system-technology co-optimization and the
inevitable need for multiphysics analysis across electrical, thermal,
mechanical, and reliability domains. We highlight how reliability and
security concerns are increasingly shaping architectural and packaging
choices, and we discuss the role of deep learning as a practical enabler
for faster simulation and design-space exploration under rising
complexity.
UID:DATE-FS03-20260421T083000-20260421T100000
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