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DTSTART;TZID=Europe/Paris:20250402T083000
DTEND;TZID=Europe/Paris:20250402T123000
LOCATION:St Clair 2
CREATED:20250320T120824
DTSTAMP:20250320T120824
SUMMARY:W07 Designing Sustainable Intelligent Systems: Integrating Carbon Footprint Reduction, TinyML, and RISC-V
URL;VALUE=URI:https://date25.date-conference.com/programme#W07
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DESCRIPTION:Get the latest session information at 
	https://date25.date-conference.com/programme#W07\n\n\nOrganisers\n	\n	-  
	Jose Miranda, ESL, EPFL, CH\n	-  Andrés Otero, University Polytechnic of 
	Madrid, ES\n	-  Alfonso Rodriguez, Universidad Politécnica de Madrid, 
	ES\n	-  Alessio Burrello, Polytechnic of Turin, IT\n	-  Daniele Pagliari, 
	Polytechnic of Turin, IT\n	-  Maurizio Martina, Polytechnic of Turin, 
	IT\n	-  Davide Schiavone, OpenHW Group, IT\n	-  Miguel Peón-Quirós, 
	EPFL, CH\n	-  David Atienza, EPFL, CH\n	\n	Keynote Speakers\n	\n	-  Danilo 
	Pau, STMicroelectronics, IT\n	-  Alberto Fernandez, INTERA Group, 
	ES\n	\n	As the world advances towards a more interconnected future with 
	smarter sensors and devices, the convergence of embedded Artificial 
	Intelligence (AI), represented by frameworks such as TinyML, open-source 
	hardware architectures like RISC-V, and sustainability considerations, 
	becomes increasingly vital. Designing systems with these three pillars in 
	mind—Carbon Footprint reduction, TinyML, and RISC-V—has profound 
	implications for creating more sustainable and energy-efficient 
	intelligent systems. Closed and proprietary solutions often limit 
	innovation and prevent the integration of eco-friendly practices by 
	restricting access to foundational technologies. In contrast, open-source 
	initiatives within the RISC-V ecosystem empower academia and industry to 
	collaborate on developing energy-efficient solutions that align with 
	global sustainability goals.\n	\n	This workshop delves into the 
	intersection of these three critical areas:\n	\n	-  Carbon Footprint 
	Reduction: Addressing the urgent need to minimise the environmental impact 
	of digital systems through sustainable design practices.\n	-  TinyML: 
	Leveraging Tiny Machine Learning to enable AI capabilities on 
	resource-constrained devices, optimising performance while reducing energy 
	consumption (particularly on data communication to the cloud or external 
	elements distant from concerning the location where sensing data is 
	collected).\n	-  RISC-V: Utilising the open-source RISC-V architecture to 
	foster innovation in hardware design, allowing for customization and 
	optimization towards energy efficiency.\n	\n	By integrating these domains, 
	participants will explore how to design and implement intelligent systems 
	that are not only powerful and efficient but also environmentally 
	responsible.\n	\n	Key Objectives of the Workshop:\n	\n	-  Interlinking the 
	Three Pillars: Understand how the combination of Carbon Footprint 
	considerations, TinyML, and RISC-V can lead to the development of 
	sustainable intelligent systems.\n	-  Innovative Solutions for 
	Sustainability: Explore methodologies and technologies that reduce energy 
	consumption and environmental impact without compromising system 
	performance.\n	-  Optimization of AI at the Edge: Learn about deploying 
	embedded AI using TinyML on RISC-V platforms to achieve high efficiency in 
	edge computing applications.\n	-  Collaborative Design Practices: Promote 
	interdisciplinary collaboration to share best practices, tools, and 
	techniques for integrating sustainability into system 
	design.\n	\n	Workshop Kick-off\n	\n	Session Start: Wed, 08:30\n	\n	Session 
	End: Wed, 09:00\n	\n	Speaker: Jose Miranda, ESL, EPFL, CH\n	\n	The 
	workshop begins with an introduction to the growing importance of 
	sustainability in intelligent system design. The kick-off highlights the 
	critical roles of Carbon Footprint reduction, TinyML, and RISC-V, setting 
	the stage for discussions on how these pillars drive energy-efficient and 
	eco-friendly innovations. This opening session underscores the need for 
	collaboration and open-source initiatives to meet global sustainability 
	goals while pushing the boundaries of embedded AI and hardware 
	design.\n	\n	Sustainable hybrid cloud-edge AI: Opportunities and 
	challenges in HW/SW\n	\n	Session Start: Wed, 09:00\n	\n	Session End: Wed, 
	09:30\n	\n	Speaker: Miguel Peón-Quirós, EPFL, CH\n	\n	Achieving a truly 
	sustainable AI continuum requires a holistic approach, where both cloud 
	and edge infrastructures are designed with efficiency in mind. This 
	session highlights the EcoCloud initiative at EPFL, showcasing how it 
	serves as a living example of sustainability in cloud computing. We will 
	discuss how sustainability principles must be integrated at every 
	level—from hardware and system design to software optimization—to 
	build energy-efficient hybrid cloud-edge AI systems. A key focus will be 
	on EcoCloud's experimental facility, which provides a sustainable 
	playground for researchers and industry partners to test and validate 
	novel hardware-software co-design approaches. This facility enables 
	real-world experimentation on energy-efficient architectures, allowing us 
	to push the boundaries of sustainable AI. The talk will also emphasize how 
	these technologies can be leveraged to create scalable, low-power, and 
	environmentally responsible AI solutions. Attendees will be encouraged to 
	actively engage in discussions, making this an interactive 
	session.\n	\n	MYRTUS: Advancing Sustainable and Secure Computing with 
	RISC-V\n	\n	Session Start: Wed, 09:30\n	\n	Session End: Wed, 
	10:00\n	\n	Speaker: Andrés Otero, University Polytechnic of Madrid, 
	ES\n	\n	The MYRTUS project is paving the way for a more secure, 
	sustainable, and efficient computing ecosystem by leveraging RISC-V and 
	open-source hardware. In this session, we will explore how MYRTUS 
	addresses challenges in trustworthy computing and energy-efficient 
	architectures, focusing on its impact on edge AI, security, and 
	sustainability. Join us to discover how this project shapes the future of 
	hardware-software co-design for next-generation applications. (MYRTUS is 
	funded by the European Union, by grant No. 101135183)\n	\n	Pushing TinyML 
	Forward: End-to-end In-Memory RISC-V Computing\n	\n	Session Start: Wed, 
	10:30\n	\n	Session End: Wed, 11:00\n	\n	Speaker: Alessio Burrello, 
	Polytechnic of Turin, IT\n	\n	In this talk, we will first describe a novel 
	hardware architecture that merges in-memory computing with a RISC-V core 
	to significantly reduce energy consumption and latency for TinyML tasks. 
	Then, we detail MATCH, a flexible compiler, built on the TVM framework, 
	designed to optimize AI workloads across heterogeneous edge systems 
	prioritizing efficiency. Finally, we will demonstrate the full pipeline by 
	deploying a deep neural network onto the presented hardware using MATCH, 
	showcasing the flexibility of the compilation tool and the efficiency of 
	the in-memory accelerator.\n	\n	The transition from Tiny ML to Edge 
	GenAI\n	\n	Session Start: Wed, 11:00\n	\n	Session End: Wed, 
	11:30\n	\n	Speaker: Danilo Pau, STMicroelectronics, IT\n	\n	Generative AI 
	(GenAI) models are designed to produce realistic and natural data, such as 
	images, audio, or written text. Due to their high computational and memory 
	demands, these models traditionally run on powerful remote computing 
	servers. However, there is growing interest in deploying GenAI models at 
	the edge, on resource-constrained embedded devices. Since 2018, the TinyML 
	community has proved that running fixed topology AI models on edge devices 
	offers several benefits, including independence from the Internet 
	connectivity, low-latency processing, and enhanced privacy. Nevertheless, 
	deploying resource-consuming GenAI models on embedded devices is 
	challenging since the latter have limited computational, memory, and 
	energy resources. This talk reviews several papers about the progress made 
	to date in the field of Edge GenAI, an emerging area of research within 
	the broader domain of EdgeAI which focuses on bringing GenAI to edge 
	devices. Papers released between 2022 and 2024 that addressed the design 
	and deployment of GenAI models on embedded devices have been identified 
	and described. Additionally, their approaches and results have been 
	compared. These manuscripts contribute to understanding the ongoing 
	transition from TinyML to Edge GenAI, providing the AI research community 
	valuable insights into this emerging and impactful, quite under-explored 
	field. Further examples of Edge GenAI will prove that some of these 
	workloads can run on existing ST MCU and MPU processors, thus showing the 
	EdgeGenAI research field is in active development.\n	\n	An SME journey on 
	AI from Cloud 2 Edge\n	\n	Session Start: Wed, 11:30\n	\n	Session End: Wed, 
	12:00\n	\n	Speaker: Alberto Fernandez, INTERA Group, ES\n	\n	At INTERA we 
	are committed to offering a complete IoT stack, from cloud to edge. At the 
	foundation of the company, we started to work on the development of a 
	proprietary IoT platform, oriented towards the EDGE, i.e. towards 
	communication and control of remote devices. The natural evolution of the 
	platform was the inclusion of AI capabilities, providing execution of 
	models at the cloud level, including automated training and deployment 
	based on continuously acquired data. Recently we started the journey 
	towards the execution of artificial intelligence models at the edge, the 
	so-called EDGE AI, incorporating and adapting open source TinyML/RISC-V 
	worldwide resources, paving the foundation for the development of our own 
	hardware and associated toolchain at an affordable pace. TinyML/RISC-V 
	allows us to co-develop optimised hardware and AI models, connecting them 
	to INTERA's (or third-party) cloud services and products to offer a 
	"full-stack" AI solution. The goal of this journey is to offer 
	technologies and solutions that impact sustainability.\n	\n	Roundtable 
	discussion: Future Directions in Sustainable Intelligent 
	Systems\n	\n	Session Start: Wed, 12:00\n	\n	Session End: Wed, 
	12:30\n	\n	Moderator: Jose Miranda, ESL, EPFL, CH\n	\n	The final session 
	of the workshop will be an interactive roundtable discussion, bringing 
	together experts and attendees to reflect on key insights from the day’s 
	talks. This session will focus on identifying open challenges, future 
	research directions, and collaborative opportunities at the intersection 
	of sustainability-enabling technologies. Participants will have the 
	opportunity to engage directly with speakers and panellists, discussing 
	how the workshop's key themes can drive innovation in embedded AI and 
	eco-friendly computing.
X-ALT-DESC;FMTTYPE=text/html:<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"><HTML><HEAD><META 
	NAME="Generator" CONTENT="MS Exchange Server version 
	16.0.17231.20290"><TITLE></TITLE></HEAD><BODY><p>Get the latest session 
	information at <a 
	href="https://date25.date-conference.com/programme#W07">https://date25.date-conference.com/programme#W07</a></p><p> 
	   Organisers</p><ul>    <li>        Jose Miranda, ESL, EPFL, CH    </li>  
	  <li>        Andrés Otero, University Polytechnic of Madrid, ES    </li> 
	   <li>        Alfonso Rodriguez, Universidad Politécnica de Madrid, ES   
	 </li>    <li>        Alessio Burrello, Polytechnic of Turin, IT    </li>  
	  <li>        Daniele Pagliari, Polytechnic of Turin, IT    </li>    <li>  
	      Maurizio Martina, Polytechnic of Turin, IT    </li>    <li>        
	Davide Schiavone, OpenHW Group, IT    </li>    <li>        Miguel 
	Peón-Quirós, EPFL, CH    </li>    <li>        David Atienza, EPFL, CH    
	</li></ul><p>    Keynote Speakers</p><ul>    <li>        Danilo Pau, 
	STMicroelectronics, IT    </li>    <li>        Alberto Fernandez, INTERA 
	Group, ES    </li></ul><p>    As the world advances towards a more 
	interconnected future with smarter sensors and devices, the convergence of 
	embedded Artificial Intelligence (AI), represented by frameworks such as 
	TinyML, open-source hardware architectures like RISC-V, and sustainability 
	considerations, becomes increasingly vital. Designing systems with these 
	three pillars in mind—Carbon Footprint reduction, TinyML, and 
	RISC-V—has profound implications for creating more sustainable and 
	energy-efficient intelligent systems. Closed and proprietary solutions 
	often limit innovation and prevent the integration of eco-friendly 
	practices by restricting access to foundational technologies. In contrast, 
	open-source initiatives within the RISC-V ecosystem empower academia and 
	industry to collaborate on developing energy-efficient solutions that 
	align with global sustainability goals.</p><p>    This workshop delves 
	into the intersection of these three critical areas:</p><ol>    <li>       
	 Carbon Footprint Reduction: Addressing the urgent need to minimise the 
	environmental impact of digital systems through sustainable design 
	practices.    </li>    <li>        TinyML: Leveraging Tiny Machine 
	Learning to enable AI capabilities on resource-constrained devices, 
	optimising performance while reducing energy consumption (particularly on 
	data communication to the cloud or external elements distant from 
	concerning the location where sensing data is collected).    </li>    <li> 
	       RISC-V: Utilising the open-source RISC-V architecture to foster 
	innovation in hardware design, allowing for customization and optimization 
	towards energy efficiency.    </li></ol><p>    By integrating these 
	domains, participants will explore how to design and implement intelligent 
	systems that are not only powerful and efficient but also environmentally 
	responsible.</p><h3>    Key Objectives of the Workshop:</h3><ul>    <li>   
	     Interlinking the Three Pillars: Understand how the combination of 
	Carbon Footprint considerations, TinyML, and RISC-V can lead to the 
	development of sustainable intelligent systems.    </li>    <li>        
	Innovative Solutions for Sustainability: Explore methodologies and 
	technologies that reduce energy consumption and environmental impact 
	without compromising system performance.    </li>    <li>        
	Optimization of AI at the Edge: Learn about deploying embedded AI using 
	TinyML on RISC-V platforms to achieve high efficiency in edge computing 
	applications.    </li>    <li>        Collaborative Design Practices: 
	Promote interdisciplinary collaboration to share best practices, tools, 
	and techniques for integrating sustainability into system design.    
	</li></ul><h4>    Workshop Kick-off</h4><p>    Session Start: Wed, 
	08:30</p><p>    Session End: Wed, 09:00</p><p>    Speaker: Jose Miranda, 
	ESL, EPFL, CH</p><p>    The workshop begins with an introduction to the 
	growing importance of sustainability in intelligent system design. The 
	kick-off highlights the critical roles of Carbon Footprint reduction, 
	TinyML, and RISC-V, setting the stage for discussions on how these pillars 
	drive energy-efficient and eco-friendly innovations. This opening session 
	underscores the need for collaboration and open-source initiatives to meet 
	global sustainability goals while pushing the boundaries of embedded AI 
	and hardware design.</p><h4>    Sustainable hybrid cloud-edge AI: 
	Opportunities and challenges in HW/SW</h4><p>    Session Start: Wed, 
	09:00</p><p>    Session End: Wed, 09:30</p><p>    Speaker: Miguel 
	Peón-Quirós, EPFL, CH</p><p>    Achieving a truly sustainable AI 
	continuum requires a holistic approach, where both cloud and edge 
	infrastructures are designed with efficiency in mind. This session 
	highlights the EcoCloud initiative at EPFL, showcasing how it serves as a 
	living example of sustainability in cloud computing. We will discuss how 
	sustainability principles must be integrated at every level—from 
	hardware and system design to software optimization—to build 
	energy-efficient hybrid cloud-edge AI systems. A key focus will be on 
	EcoCloud's experimental facility, which provides a sustainable playground 
	for researchers and industry partners to test and validate novel 
	hardware-software co-design approaches. This facility enables real-world 
	experimentation on energy-efficient architectures, allowing us to push the 
	boundaries of sustainable AI. The talk will also emphasize how these 
	technologies can be leveraged to create scalable, low-power, and 
	environmentally responsible AI solutions. Attendees will be encouraged to 
	actively engage in discussions, making this an interactive 
	session.</p><h4>    MYRTUS: Advancing Sustainable and Secure Computing 
	with RISC-V</h4><p>    Session Start: Wed, 09:30</p><p>    Session End: 
	Wed, 10:00</p><p>    Speaker: Andrés Otero, University Polytechnic of 
	Madrid, ES</p><p>    The MYRTUS project is paving the way for a more 
	secure, sustainable, and efficient computing ecosystem by leveraging 
	RISC-V and open-source hardware. In this session, we will explore how 
	MYRTUS addresses challenges in trustworthy computing and energy-efficient 
	architectures, focusing on its impact on edge AI, security, and 
	sustainability. Join us to discover how this project shapes the future of 
	hardware-software co-design for next-generation applications. (MYRTUS is 
	funded by the European Union, by grant No. 101135183)</p><h4>    Pushing 
	TinyML Forward: End-to-end In-Memory RISC-V Computing</h4><p>    Session 
	Start: Wed, 10:30</p><p>    Session End: Wed, 11:00</p><p>    Speaker: 
	Alessio Burrello, Polytechnic of Turin, IT</p><p>    In this talk, we will 
	first describe a novel hardware architecture that merges in-memory 
	computing with a RISC-V core to significantly reduce energy consumption 
	and latency for TinyML tasks. Then, we detail MATCH, a flexible compiler, 
	built on the TVM framework, designed to optimize AI workloads across 
	heterogeneous edge systems prioritizing efficiency. Finally, we will 
	demonstrate the full pipeline by deploying a deep neural network onto the 
	presented hardware using MATCH, showcasing the flexibility of the 
	compilation tool and the efficiency of the in-memory accelerator.</p><h4>  
	  The transition from Tiny ML to Edge GenAI</h4><p>    Session Start: Wed, 
	11:00</p><p>    Session End: Wed, 11:30</p><p>    Speaker: Danilo Pau, 
	STMicroelectronics, IT</p><p>    Generative AI (GenAI) models are designed 
	to produce realistic and natural data, such as images, audio, or written 
	text. Due to their high computational and memory demands, these models 
	traditionally run on powerful remote computing servers. However, there is 
	growing interest in deploying GenAI models at the edge, on 
	resource-constrained embedded devices. Since 2018, the TinyML community 
	has proved that running fixed topology AI models on edge devices offers 
	several benefits, including independence from the Internet connectivity, 
	low-latency processing, and enhanced privacy. Nevertheless, deploying 
	resource-consuming GenAI models on embedded devices is challenging since 
	the latter have limited computational, memory, and energy resources. This 
	talk reviews several papers about the progress made to date in the field 
	of Edge GenAI, an emerging area of research within the broader domain of 
	EdgeAI which focuses on bringing GenAI to edge devices. Papers released 
	between 2022 and 2024 that addressed the design and deployment of GenAI 
	models on embedded devices have been identified and described. 
	Additionally, their approaches and results have been compared. These 
	manuscripts contribute to understanding the ongoing transition from TinyML 
	to Edge GenAI, providing the AI research community valuable insights into 
	this emerging and impactful, quite under-explored field. Further examples 
	of Edge GenAI will prove that some of these workloads can run on existing 
	ST MCU and MPU processors, thus showing the EdgeGenAI research field is in 
	active development.</p><h4>    An SME journey on AI from Cloud 2 
	Edge</h4><p>    Session Start: Wed, 11:30</p><p>    Session End: Wed, 
	12:00</p><p>    Speaker: Alberto Fernandez, INTERA Group, ES</p><p>    At 
	INTERA we are committed to offering a complete IoT stack, from cloud to 
	edge. At the foundation of the company, we started to work on the 
	development of a proprietary IoT platform, oriented towards the EDGE, i.e. 
	towards communication and control of remote devices. The natural evolution 
	of the platform was the inclusion of AI capabilities, providing execution 
	of models at the cloud level, including automated training and deployment 
	based on continuously acquired data. Recently we started the journey 
	towards the execution of artificial intelligence models at the edge, the 
	so-called EDGE AI, incorporating and adapting open source TinyML/RISC-V 
	worldwide resources, paving the foundation for the development of our own 
	hardware and associated toolchain at an affordable pace. TinyML/RISC-V 
	allows us to co-develop optimised hardware and AI models, connecting them 
	to INTERA's (or third-party) cloud services and products to offer a 
	"full-stack" AI solution. The goal of this journey is to offer 
	technologies and solutions that impact sustainability.</p><h4>    
	Roundtable discussion: Future Directions in Sustainable Intelligent 
	Systems</h4><p>    Session Start: Wed, 12:00</p><p>    Session End: Wed, 
	12:30</p><p>    Moderator: Jose Miranda, ESL, EPFL, CH</p><p>    The final 
	session of the workshop will be an interactive roundtable discussion, 
	bringing together experts and attendees to reflect on key insights from 
	the day’s talks. This session will focus on identifying open challenges, 
	future research directions, and collaborative opportunities at the 
	intersection of sustainability-enabling technologies. Participants will 
	have the opportunity to engage directly with speakers and panellists, 
	discussing how the workshop's key themes can drive innovation in embedded 
	AI and eco-friendly computing.</p></BODY></HTML>
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