BEGIN:VCALENDAR VERSION:2.0 PRODID:-//DATE2025//date-conference.com//EN CALSCALE:GREGORIAN METHOD:PUBLISH BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20250401T140000 DTEND;TZID=Europe/Paris:20250401T180000 LOCATION:St Clair 2 CREATED:20250320T120824 DTSTAMP:20250320T120824 SUMMARY:W06 Cross-stack Explorations of Ferroelectric-based Logic and Memory Solutions for At-Scale Compute Workloads URL;VALUE=URI:https://date25.date-conference.com/programme#W06 BEGIN:VALARM TRIGGER:-PT15M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM DESCRIPTION:Get the latest session information at https://date25.date-conference.com/programme#W06\n\n\nGeneral Co-Chairs\n \n - Ian O'Connor, École Centrale de Lyon, FR\n - Stefan Slesazeck, NaMLab, DE\n \n Programme Co-Chairs\n \n - Michael Niemier, University of Notre Dame, US\n - Xunzhao Yin, Zhejiang University, CN\n \n This workshop will speak to research with respect to ferroelectrics at all levels of the design stack.\n \n - It will begin by discussing ferroelectric device concepts (e.g., front end of line (FEOL) and back end of line (BEOL) ferroelectric field effect transistors (FeFETs), ferro-based NAND, FeRAM, etc. as well as modeling efforts).\n - Talks will effectively consider ferroelectrics from the “bottom-up” by addressing (a) how materials-based design-levers may influence device behavior (i.e., how might we optimize a device for a figure of merit that most benefits an application-level workload) and (b) new research in AI-guided materials discovery.\n - Subsequently, talks will consider the use of ferroelectric devices in novel circuits and/or memory architectures (e.g., associative memories, crossbar-based structures, and ferroelectric solutions where computation is done via charge sharing).\n - Novel algorithmic solutions based on ferroelectric devices, as well as how one might develop compiler support for technology-enabled, IMC solutions will also be discussed.\n \n This workshop will include a submission-based poster-session to maximize engagement from the DATE community.\n \n Ferroelectric Device Concepts, Modeling, and Materials\n \n Session Start: Tue, 14:00\n \n Session End: Tue, 16:00\n \n Session chair: Michael Niemier, University of Notre Dame, US\n \n This session begins with discussions of various ferroelectric device concepts including front-end-of-line (FEOL) and back-end-of-line (BEOL) ferroelectric field effect transistors (FeFET), ferro-based NAND memory, ferroelectric random access memory (FeRAM), and ferroelectric tunneling junctions (FTJs). Modeling efforts, as well as how artificial intelligence might be used for material science-based design space explorations will also be discussed.\n \n Presentations\n \n Enabling AI Computing Applications with Novel Ferroelectric Devices\n \n Start: 14:00\n \n End: 14:20\n \n Speaker: Milind Weling, EMD Performance Materials, US\n \n Artificial intelligence (AI) is clearly a transformative force reshaping our technological landscape and igniting a surge of interest in disruptive innovations across all levels of abstraction. As we stand on the brink of an AI revolution, the demand for advanced computing capabilities is skyrocketing. Yet, traditional memory solutions like on-chip SRAM and off-chip DRAM are struggling to keep up, creating a critical bottleneck that can impede the AI juggernaut. Imagine the possibilities if we could achieve over 100X improvements in memory density, bandwidth, latency, performance, and energy efficiency! This isn't just a dream—it's an urgent necessity for the future of AI. Enter ferroelectric devices, which hold incredible potential when co-optimized for key parameter indices (KPIs) across system, design, device, technology and materials. This talk will explore the exciting opportunities and formidable challenges that lie ahead as we transition from established memory devices, technologies and materials to novel ones. Join this journey as we envision a future where memory technology not only supports but accelerates the AI revolution!\n \n Ferro-based NAND\n \n Start: 14:20\n \n End: 14:40\n \n Speaker: Asif Khan, Georgia Institute of Technology, US\n \n FeRAM\n \n Start: 14:40\n \n End: 15:00\n \n Speaker: Laurent Grenouillet, CEA-Leti, FR\n \n Perovskite-based Ferroelectric Random Access Memories (FeRAM) cannot scale beyond 130nm and offer poor CMOS compatibility. The discovery of hafnia-zirconia-based films changed FeRAM paradigm about 15 years ago. This talk will cover HZO-based FeRAM demonstrations from 130nm down to 22nm node, highlighting the opportunities and challenges related to this promising technology.\n \n Prospects of Ferroelectric Tunneling Junctions\n \n Start: 15:00\n \n End: 15:20\n \n Speaker: Stefan Slesazeck, NaMLab, DE\n \n Ferroelectric tunneling junctions (FTJ) are 2-terminal non-volatile memory devices, that consist of an active ferroelectric layer or multi-layer stack which is sandwiched between two metallic or semiconducting electrodes. In these devices the non-destructive read operation bases on the modulation of the tunneling current by the polarization state of the ferroelectric layer. Due to their high-impedance and rectifying properties FTJs are interesting candidates for the implementation of selector-less passive cross-bar arrays and for massive parallel readout for the realization of MVM in scalable selector-less passive cross-bar arrays. In this talk I will introduce the concept of the FTJ devices and discuss the prospects for their adoption in memory applications and beyond.\n \n Modeling Ferroelectric Devices\n \n Start: 15:20\n \n End: 15:40\n \n Speaker: Hussam Amrouch, Technical University Munich, DE\n \n Ferroelectric Field-Effect Transistors (FeFETs) are a promising technology with immense potential for in-memory computing and AI acceleration. However, modeling their reliability remains a significant challenge due to multiple sources of variability. Design-time variability from process variations, run-time fluctuations driven by temperature effects, and the inherent stochasticity of ferroelectric domain switching—rooted in its probabilistic nature—make accurate reliability prediction highly complex. Without robust reliability models, it is impossible to ensure the accuracy and dependability of FeFET-based AI accelerator systems, which directly impacts the precision and effectiveness of AI algorithms. This talk presents a holistic framework for reliability estimation, seamlessly integrating insights from device physics to circuit-level analysis. We also highlight the transformative role of deep learning in addressing these challenges, demonstrating how it enables precise reliability modeling and unlocks the full potential of FeFET technology for next-generation computing.\n \n AI Guided Materials Discovery\n \n Start: 15:40\n \n End: 16:00\n \n Speaker: Christopher Hinkle, University of Notre Dame, US\n \n This talk will discuss strategies to implement an accelerated discovery and codesign platform for efficient design and discovery of new ferroelectric materials and their properties in relevant devices. Achieving this goal requires moving beyond conventional, linear approaches to materials discovery, transforming them into a cyclic and iterative process integrating computation, experiment, and theory to formulate the processing-structure-property-performance relationships necessary to advance ferroelectric materials and devices. We will describe our progress in using machine learning to automate and accelerate materials characterization leading to adaptive learning for simulation and high-throughput synthesis and characterization.\n \n Poster Session\n \n Session Start: Tue, 16:00\n \n Session End: Tue, 16:40\n \n Posters Chair: Ian O'Connor, École Centrale de Lyon, FR\n \n Architectures, Applications, and Compilation Techniques for Ferroelectric Devices\n \n Session Start: Tue, 16:40\n \n Session End: Tue, 18:00\n \n Session chair: Michael Niemier, University of Notre Dame , US\n \n This session begins by considering in-memory computing (IMC) solutions based on ferroelectric device concepts. Recent work with respect to ferroelectric content addressable memories, crossbar arrays, as well as charge sharing architectures (that can also perform associative memory and MAC operations) will all be discussed. The session concludes with a discussion of recent work relating to compilation techniques and higher-level programming abstractions for ferroelectric IMC solutions.\n \n Presentations\n \n Ferroelectric Solutions for Content Addressable Memories\n \n Start: 16:40\n \n End: 17:00\n \n Speaker: Xunzhao Yin, Zhejiang University, CN\n \n Ferroelectric Nonvolatile Capacitor (nvCap) for Charge Domain Compute-in-Memory\n \n Start: 17:00\n \n End: 17:20\n \n Speaker: Shimeng Yu, Georgia Institute of Technology, US\n \n Non-volatile ferroelectric capacitor (nvCap) that leverages the small-signal non-destructive read is a new concept to the ferroelectric memory family. nvCap overcomes the endurance limitation imposed by the destructive read in conventional ferroelectric random access memory (FeRAM) that relies on large-signal polarization switching. nvCap is also a promising candidate to enable the charge domain computation in a capacitive crossbar array for in-memory computing that only consumes dynamic power. The key engineering goal of nvCap is to optimize a asymmetric C-V characteristics to open up the large capacitance on/off ratio at DC zero voltage. In this talk, we present the progresses of our work on optimizing the nvCap device. We first introduce the HZO-based MFM nvCap that demonstrates the proof-of-concept, and present the FeFET-based MFS nvCap that improves capacitance on/off ratio with reliability/scaling analysis. Finally we report our new results on BEOL-compatible MFS nvCap based on a oxide semiconductor layer.\n \n Charge Sharing Architectures with Ferroelectric Devices\n \n Start: 17:20\n \n End: 17:40\n \n Speaker: Thomas Kämpfe, Fraunhofer IPMS, DE\n \n This talk introduces the possibility of charge-domain computing using a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET). This cell operating in the charge domain is marking a significant advancement for compute-in-memory (CIM) which improves the energy efficiency but also robustness due to the low capacitor mismatch. Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.\n \n Compiler Support for Ferroelectric Compute-in-Memory Solutions (and beyond)\n \n Start: 17:40\n \n End: 18:00\n \n Speaker: Jeronimo Castrillon, TU Dresden, DE\n \n Compute-in-Memory (CIM) is a promising non-von Neumann computing paradigm that promises unprecedented improvements in performance and energy efficiency. Moving past manual designs, automation will be key to unleash the potential of CIM for multiple application domains and to accelerate cross-layer design cycles. This talks reports on an ongoing effort to build a high-level compiler infrastructure for different CIM approaches, built with MLIR to abstract from individual technologies to foster re-use. This includes abstractions and optimizations flows for logic-in memory, content-addressable memories, arithmetic operations in crossbars, and near-memory architectures. We also report on recent results retargeting the compiler for novel ferroelectric cells, exploring different memory modalities. X-ALT-DESC;FMTTYPE=text/html:

Get the latest session information at https://date25.date-conference.com/programme#W06

General Co-Chairs

Programme Co-Chairs

This workshop will speak to research with respect to ferroelectrics at all levels of the design stack.

This workshop will include a submission-based poster-session to maximize engagement from the DATE community.

Ferroelectric Device Concepts, Modeling, and Materials

Session Start: Tue, 14:00

Session End: Tue, 16:00

Session chair: Michael Niemier, University of Notre Dame, US

This session begins with discussions of various ferroelectric device concepts including front-end-of-line (FEOL) and back-end-of-line (BEOL) ferroelectric field effect transistors (FeFET), ferro-based NAND memory, ferroelectric random access memory (FeRAM), and ferroelectric tunneling junctions (FTJs). Modeling efforts, as well as how artificial intelligence might be used for material science-based design space explorations will also be discussed.

Presentations

Enabling AI Computing Applications with Novel Ferroelectric Devices

Start: 14:00

End: 14:20

Speaker: Milind Weling, EMD Performance Materials, US

Artificial intelligence (AI) is clearly a transformative force reshaping our technological landscape and igniting a surge of interest in disruptive innovations across all levels of abstraction. As we stand on the brink of an AI revolution, the demand for advanced computing capabilities is skyrocketing. Yet, traditional memory solutions like on-chip SRAM and off-chip DRAM are struggling to keep up, creating a critical bottleneck that can impede the AI juggernaut. Imagine the possibilities if we could achieve over 100X improvements in memory density, bandwidth, latency, performance, and energy efficiency! This isn't just a dream—it's an urgent necessity for the future of AI. Enter ferroelectric devices, which hold incredible potential when co-optimized for key parameter indices (KPIs) across system, design, device, technology and materials. This talk will explore the exciting opportunities and formidable challenges that lie ahead as we transition from established memory devices, technologies and materials to novel ones. Join this journey as we envision a future where memory technology not only supports but accelerates the AI revolution!

 

Ferro-based NAND

Start: 14:20

End: 14:40

Speaker: Asif Khan, Georgia Institute of Technology, US

FeRAM

Start: 14:40

End: 15:00

Speaker: Laurent Grenouillet, CEA-Leti, FR

Perovskite-based Ferroelectric Random Access Memories (FeRAM) cannot scale beyond 130nm and offer poor CMOS compatibility. The discovery of hafnia-zirconia-based films changed FeRAM paradigm about 15 years ago. This talk will cover HZO-based FeRAM demonstrations from 130nm down to 22nm node, highlighting the opportunities and challenges related to this promising technology.

Prospects of Ferroelectric Tunneling Junctions

Start: 15:00

End: 15:20

Speaker: Stefan Slesazeck, NaMLab, DE

Ferroelectric tunneling junctions (FTJ) are 2-terminal non-volatile memory devices, that consist of an active ferroelectric layer or multi-layer stack which is sandwiched between two metallic or semiconducting electrodes. In these devices the non-destructive read operation bases on the modulation of the tunneling current by the polarization state of the ferroelectric layer. Due to their high-impedance and rectifying properties FTJs are interesting candidates for the implementation of selector-less passive cross-bar arrays and for massive parallel readout for the realization of MVM in scalable selector-less passive cross-bar arrays. In this talk I will introduce the concept of the FTJ devices and discuss the prospects for their adoption in memory applications and beyond.

Modeling Ferroelectric Devices

Start: 15:20

End: 15:40

Speaker: Hussam Amrouch, Technical University Munich, DE

Ferroelectric Field-Effect Transistors (FeFETs) are a promising technology with immense potential for in-memory computing and AI acceleration. However, modeling their reliability remains a significant challenge due to multiple sources of variability. Design-time variability from process variations, run-time fluctuations driven by temperature effects, and the inherent stochasticity of ferroelectric domain switching—rooted in its probabilistic nature—make accurate reliability prediction highly complex. Without robust reliability models, it is impossible to ensure the accuracy and dependability of FeFET-based AI accelerator systems, which directly impacts the precision and effectiveness of AI algorithms. This talk presents a holistic framework for reliability estimation, seamlessly integrating insights from device physics to circuit-level analysis. We also highlight the transformative role of deep learning in addressing these challenges, demonstrating how it enables precise reliability modeling and unlocks the full potential of FeFET technology for next-generation computing.

AI Guided Materials Discovery

Start: 15:40

End: 16:00

Speaker: Christopher Hinkle, University of Notre Dame, US

This talk will discuss strategies to implement an accelerated discovery and codesign platform for efficient design and discovery of new ferroelectric materials and their properties in relevant devices. Achieving this goal requires moving beyond conventional, linear approaches to materials discovery, transforming them into a cyclic and iterative process integrating computation, experiment, and theory to formulate the processing-structure-property-performance relationships necessary to advance ferroelectric materials and devices. We will describe our progress in using machine learning to automate and accelerate materials characterization leading to adaptive learning for simulation and high-throughput synthesis and characterization.

Poster Session

Session Start: Tue, 16:00

Session End: Tue, 16:40

Posters Chair: Ian O'Connor, École Centrale de Lyon, FR

Architectures, Applications, and Compilation Techniques for Ferroelectric Devices

Session Start: Tue, 16:40

Session End: Tue, 18:00

Session chair: Michael Niemier, University of Notre Dame , US

This session begins by considering in-memory computing (IMC) solutions based on ferroelectric device concepts. Recent work with respect to ferroelectric content addressable memories, crossbar arrays, as well as charge sharing architectures (that can also perform associative memory and MAC operations) will all be discussed. The session concludes with a discussion of recent work relating to compilation techniques and higher-level programming abstractions for ferroelectric IMC solutions.

Presentations

Ferroelectric Solutions for Content Addressable Memories

Start: 16:40

End: 17:00

Speaker: Xunzhao Yin, Zhejiang University, CN

Ferroelectric Nonvolatile Capacitor (nvCap) for Charge Domain Compute-in-Memory

Start: 17:00

End: 17:20

Speaker: Shimeng Yu, Georgia Institute of Technology, US

Non-volatile ferroelectric capacitor (nvCap) that leverages the small-signal non-destructive read is a new concept to the ferroelectric memory family. nvCap overcomes the endurance limitation imposed by the destructive read in conventional ferroelectric random access memory (FeRAM) that relies on large-signal polarization switching. nvCap is also a promising candidate to enable the charge domain computation in a capacitive crossbar array for in-memory computing that only consumes dynamic power. The key engineering goal of nvCap is to optimize a asymmetric C-V characteristics to open up the large capacitance on/off ratio at DC zero voltage. In this talk, we present the progresses of our work on optimizing the nvCap device. We first introduce the HZO-based MFM nvCap that demonstrates the proof-of-concept, and present the FeFET-based MFS nvCap that improves capacitance on/off ratio with reliability/scaling analysis. Finally we report our new results on BEOL-compatible MFS nvCap based on a oxide semiconductor layer.

Charge Sharing Architectures with Ferroelectric Devices

Start: 17:20

End: 17:40

Speaker: Thomas Kämpfe, Fraunhofer IPMS, DE

This talk introduces the possibility of charge-domain computing using a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET). This cell operating in the charge domain is marking a significant advancement for compute-in-memory (CIM) which improves the energy efficiency but also robustness due to the low capacitor mismatch. Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.

Compiler Support for Ferroelectric Compute-in-Memory Solutions (and beyond)

Start: 17:40

End: 18:00

Speaker: Jeronimo Castrillon, TU Dresden, DE

Compute-in-Memory (CIM) is a promising non-von Neumann computing paradigm that promises unprecedented improvements in performance and energy efficiency. Moving past manual designs, automation will be key to unleash the potential of CIM for multiple application domains and to accelerate cross-layer design cycles. This talks reports on an ongoing effort to build a high-level compiler infrastructure for different CIM approaches, built with MLIR to abstract from individual technologies to foster re-use. This includes abstractions and optimizations flows for logic-in memory, content-addressable memories, arithmetic operations in crossbars, and near-memory architectures. We also report on recent results retargeting the compiler for novel ferroelectric cells, exploring different memory modalities.

UID:DATE-W06-20250401T140000-20250401T180000 END:VEVENT BEGIN:VTIMEZONE TZID:Europe/Paris TZURL:http://tzurl.org/zoneinfo/Europe/Paris X-LIC-LOCATION:Europe/Paris BEGIN:DAYLIGHT TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST DTSTART:19810329T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CEST DTSTART:19961027T030000 RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU END:STANDARD BEGIN:STANDARD TZOFFSETFROM:-001444 TZOFFSETTO:+0000 TZNAME:WET DTSTART:19010101T000000 RDATE:19010101T000000 END:STANDARD END:VTIMEZONE END:VCALENDAR