BEGIN:VCALENDAR VERSION:2.0 PRODID:-//DATE2025//date-conference.com//EN CALSCALE:GREGORIAN METHOD:PUBLISH BEGIN:VEVENT DTSTART;TZID=Europe/Paris:20250331T110000 DTEND;TZID=Europe/Paris:20250331T123000 LOCATION:Rhône 2 CREATED:20250320T120824 DTSTAMP:20250320T120824 SUMMARY:ET01 Agile Hardware Specialization: A toolbox for Agile Chip Front-end Design URL;VALUE=URI:https://date25.date-conference.com/programme#ET01 BEGIN:VALARM TRIGGER:-PT15M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM DESCRIPTION:Get the latest session information at https://date25.date-conference.com/programme#ET01\n\n\nCompared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce Agile Hardware Specialization (AHS): A toolbox for Agile Chip Front-end Design.\n \n The tutorial will highlight the methodology and open source tools in AHS for both chip design and verification. From the design perspective, AHS presents multiple ways that use different programming interfaces and target different scenarios, including;\n \n - a multi-level hardware intermediate representation based high-level synthesis flow, which uses C and C++ as the programming language. This flow also supports domain specific language and optimization for specific domains such as tensor algebra. We also design an efficient cross-level debugger for high-level synthesis that enables breakpoints and stepping at different hardware intermediate representations.\n - an embedded hardware description language, which uses Rust as the programming language. This flow includes a general HDL and provides deterministic timing support and procedural control logic specification.\n \n These different methodologies exhibit different trade-offs in productivity and PPA (performance, power, and area) for chip design. From the verification perspective, we will present agile simulation and debugging tools, which can check the functional and performance behaviors of the hardware. The attendees will learn the methodology, design automation fundamentals, and software tools of AHS.\n \n Speakers\n \n Dr. Yun Liang, Professor, Peking University, China\n Xiaochen Hao, Ph.D Candidate, Peking University, China\n \n Target Audience\n \n We invite DATE 2025 participants with a keen interest in chip design and verification and computer-aided design (CAD) tools. Please join us!\n \n Learning objectives\n \n - An introduction to the AHS framework.\n - Details of the AHS tools including Hector, Hestia, Cement, Khronos, etc.\n - Hands-on experimentation using AHS tools.\n - Motivate future research within the AHS framework.\n \n Required Background\n \n - Basic knowledge of programming such as C or C++\n - A keen interest in learning hardware specialization and Electronic Design Automation (EDA)\n - Desirable: prior knowledge of high level synthesis and associated tool-chains.\n \n Detailed Program\n \n - Part 1: Lecture (1 hour)\n - Part 2: Hands-on session (30 mins)\n \n Lab installation instructions and handouts are available at: https://ericlyun.me/tutorial-date2025 X-ALT-DESC;FMTTYPE=text/html:

Get the latest session information at https://date25.date-conference.com/programme#ET01

Compared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce Agile Hardware Specialization (AHS): A toolbox for Agile Chip Front-end Design.

The tutorial will highlight the methodology and open source tools in AHS for both chip design and verification. From the design perspective, AHS presents multiple ways that use different programming interfaces and target different scenarios, including;

  1. a multi-level hardware intermediate representation based high-level synthesis flow, which uses C and C++ as the programming language. This flow also supports domain specific language and optimization for specific domains such as tensor algebra. We also design an efficient cross-level debugger for high-level synthesis that enables breakpoints and stepping at different hardware intermediate representations.
  2. an embedded hardware description language, which uses Rust as the programming language. This flow includes a general HDL and provides deterministic timing support and procedural control logic specification.

These different methodologies exhibit different trade-offs in productivity and PPA (performance, power, and area) for chip design. From the verification perspective, we will present agile simulation and debugging tools, which can check the functional and performance behaviors of the hardware. The attendees will learn the methodology, design automation fundamentals, and software tools of AHS.

Speakers

Dr. Yun Liang, Professor, Peking University, China
Xiaochen Hao, Ph.D Candidate, Peking University, China

Target Audience

We invite DATE 2025 participants with a keen interest in chip design and verification and computer-aided design (CAD) tools. Please join us!

Learning objectives

Required Background

Detailed Program

Lab installation instructions and handouts are available at: https://ericlyun.me/tutorial-date2025

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