BEGIN:VCALENDAR VERSION:2.0 PRODID:-//DATE2024//date-conference.com//EN CALSCALE:GREGORIAN METHOD:PUBLISH BEGIN:VEVENT DTSTART;TZID=Europe/Madrid:20240326T083000 DTEND;TZID=Europe/Madrid:20240326T123000 LOCATION:Break-Out Room S6+7 CREATED:20240322T074734 DTSTAMP:20240322T074734 SUMMARY:W02 Workshop: 3D Integration: Heterogeneous 3D Architectures and Sensors URL;VALUE=URI:https://date24.date-conference.com/programme#W02 BEGIN:VALARM TRIGGER:-PT15M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM DESCRIPTION:Get the latest session information at https://date24.date-conference.com/programme#W02\n\n\nOrganiser\n \n Pascal Vivet, CEA-LIST, France\n \n Workshop Description\n \n 3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.\n \n Technical Program\n \n Subject to final changes\n \n - 8:30 - 8:35 : Workshop Introduction, Pascal Vivet, CEA-List, FR\n - 8:35 - 9:00 : Keynote\n \n - “Enabling a Chiplet Ecosystem”, Tony Mastroianni, SIEMENS EDA, USA\n \n - 9:00 - 10:00 : Session 1 : Chiplet architecture and AI acceleration\n \n - "Occamy - A 432-Core Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support", Gianna Paulin, ETH-Z, CH (*now in AXELERA)\n - “Chiplets for future automotive application”, Andy Heinig, Fraunhofer, Dresden, DE\n - “Silicon Photonic Network-on-Interposer Design for Energy Efficient Convolutional Neural Network Acceleration on 2.5D Chiplet Platforms”, Sudeep Pasricha, Colorado State Univ, USA\n - “Multiple-Stacked-Wafer (MSW) technology : the appropriate technology for ultra-low power Smart Sensor”, Sébastien Thuriès, CEA-List and IRT-Nanoelec, FR\n \n - 10:00 - 11:00 : Coffee Break\n - 11:00 - 12:30 : Session 2 : Advanced Architectures and Thermal management\n \n - “Heterogeneous 3D integration for quantum computer chip”, Ryoichi Ishihara, TU Delft, NL\n - “Foundry Monolithic 3D Logic+Memory Stack unlocks Large IC Architectural Benefits”, Tathagata Srimani, Carnegie Mellon Univ., USA\n - “3D Evolution in Nanosheet: A Glance on General Purpose AI, Dense-XR and Edge computing”, Sudipta Das, IMEC, BE\n - “Machine Learning for Thermal Modeling of 3D Integrated Circuits”, Yuanqing Cheng, Beihang University, China\n - “Thermal Management for 3D-Stacked Processors”, Anuj Pathania, University of Amsterdam, NL\n \n - 12:30 : Closing\n \n Workshop Committee\n \n Pascal Vivet, CEA-List & IRT Nanoelec, France\n \n Gianna Paulin, ETH-Z, Switzerland\n \n Peter Ramm, Fraunhofer EMFT, Germany\n \n Mustafa Badaroglu, QUALCOMM, United States\n \n Subhasish Mitra, Stanford University, United States\n \n Past editions\n \n The 3D Integration workshop took place from 2009 to 2015 and restarted in 2022.\n \n - DATE 2009: https://past.date-conference.com/date09/conference/workshop-W5\n - DATE 2010: https://past.date-conference.com/date10/conference/workshop-W5\n - DATE 2011: https://past.date-conference.com/date11/conference/workshop-W5\n - DATE 2012: https://past.date-conference.com/date12/conference/workshop-W5\n - DATE 2013: https://past.date-conference.com/date13/conference/workshop-W5\n - DATE 2014: https://past.date-conference.com/date14/conference/workshop-W5\n - DATE 2015: https://past.date-conference.com/date15/conference/workshop-W05\n - DATE 2022: https://date22.date-conference.com/workshop/w02\n - DATE 2023: https://date23.date-conference.com/workshop/w02 X-ALT-DESC;FMTTYPE=text/html:

Get the latest session information at https://date24.date-conference.com/programme#W02

Organiser

Pascal Vivet, CEA-LIST, France

Workshop Description

3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.

Technical Program

Subject to final changes

Workshop Committee

Pascal Vivet, CEA-List & IRT Nanoelec, France

Gianna Paulin, ETH-Z, Switzerland

Peter Ramm, Fraunhofer EMFT, Germany

Mustafa Badaroglu, QUALCOMM, United States

Subhasish Mitra, Stanford University, United States

Past editions

The 3D Integration workshop took place from 2009 to 2015 and restarted in 2022.

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